Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user to perform specified logic functions. One type of PLD, the complex programmable logic device (CPLD), typically includes a group of input/output (I/O) cells, a corresponding set of programmable function blocks, and an interconnect matrix called a switch matrix. The I/O cells provide communication between the CPLD and other devices or systems. The function blocks generate a plurality of P-terms (product terms) and, from these P-terms, one or more SOP (sum of products) output signals. The switch matrix provides internal communication between and among the function blocks and I/O cells.
The functionality of the I/O cells, the function blocks, and the switch matrix is controlled by data bits stored in memory cells also included in the CPLD. Therefore, the functionality of the CPLD is defined by writing data values into these memory cells. This process is called “programming” or “configuration”, and the data values written to the memory cells are called “programming data” or “configuration data”. CPLDs are non-volatile devices, meaning that a CPLD, once programmed, need not be reprogrammed after power is removed from and restored to the device.
One known variety of CPLDs is the “CoolRunner™” CPLD family manufactured by Xilinx, Inc. CoolRunner devices are described in pages 6-1 through 6-13 of “The Programmable Logic Data Book 2000”, available from Xilinx, Inc., of San Jose, Calif., which pages are incorporated herein by reference.
CoolRunner CPLDs are low-power devices that incorporate a number of features designed to reduce power consumption in the device. One such feature is the inclusion of two sets of memory cells, one non-volatile (as in other CPLDs) and one volatile. When the device is programmed, as in other CPLDs, the programming data is written to a group of non-volatile memory cells. However, these non-volatile memory cells do not directly control the functionality of the device. Instead, when the device is inserted in a system and power is applied, the programming data is copied from the non-volatile memory cells to a group of volatile memory cells. It is the data in these volatile memory cells that controls the functionality of the I/O cells, the function blocks, and the switch matrix in CoolRunner CPLDs. Because volatile memory consumes less power than similarly-loaded non-volatile memory, this unique architectural feature contributes to the low power consumption of the CoolRunner devices.
However, this data transfer may not be error-free if the data transfer occurs when the supply voltage is either too low or too noisy.
One known method to reduce or eliminate errors caused by a low supply voltage is to include safeguards in the CPLD to hold off the data transfer until a minimum supply voltage is reached. For example, a reference circuit such as a bandgap circuit or a diode stack can be used to set a minimum supply voltage. However, system supply voltages are dropping, e.g., from 3.3 volts to 1.8 volts to 1.5 volts and below. As they drop, the margin between the system supply voltage and a controllable minimum supply voltage is reduced to the point where temperature variations and silicon manufacturing tolerances render the difference negligible. Under certain conditions, and given a sufficiently low system supply voltage, there may be cases where data transfer from non-volatile to volatile memory is not triggered at all.
Errors caused by a noisy supply voltage can also be problematical. While ramping up, the supply voltage can rise above the minimum supply voltage, triggering the memory transfer, then “glitch” low, momentarily falling back below the minimum supply voltage. If this glitch is undetected, faulty data can be loaded into one or more volatile memory cells. Most problematic is the transfer of programmed (low, or conducting) values. When the supply voltage drops below the minimum supply voltage, the data transfers as erased (high, or non-conducting) data.
In some CPLDs, the minimum supply voltage signal is gated by another signal that senses the supply voltage is high enough to permit non-volatile to volatile memory data transfer. However, this arrangement only detects the supply voltage at the beginning of the data transfer. (This solution is similar to the well-known technique of supplying a “dummy word” in a memory array, which is used to test the memory functionality.) If the supply voltage drops at any time during the memory transfer, even if only transiently, data transfer errors can occur.
Therefore, it is desirable to introduce structures and methods that reduce the incidence of data transfer errors between non-volatile and volatile memory.